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1 for more information www.analog.com document feedback typical application features description octal, 12-bit + sign, 1.5msps/ch simultaneous sampling adc the lt c ? 2320-12 is a low noise, high speed octal 12 - bit + sign successive approximation register (sar) adc with differential inputs and wide input common mode range. operating from a single 3.3v or 5v supply, the ltc2320 - 12 has an 8v p-p differential input range, making it ideal for applications which require a wide dynamic range with high common mode rejection. the LTC2320-12 achieves 0.25lsb inl typical, no missing codes at 12 bits and 77db snr. the ltc2320 -12 has an onboard low drift ( 20ppm / c max) 2.048v or 4.096v temperature-compensated reference. the ltc2320 -12 also has a high speed spi-compatible serial interface that supports cmos or lvds. the fast 1.5msps per channel throughput with no latency makes the ltc2320 -12 ideally suited for a wide variety of high speed applications. the LTC2320-12 dissipates only 20mw per channel and offers nap and sleep modes to reduce the power consumption to 26w for further power savings during inactive periods. 32k point fft f smpl = 1.5msps, f in = 500khz applications n 1.5msps/ch throughput rate n eight simultaneously sampling channels n guaranteed 12-bit, no missing codes n 8v p-p differential inputs with wide input common mode range n 77db snr (typ) at f in = 500khz n C90db thd (typ) at f in = 500khz n guaranteed operation to 125c n single 3.3v or 5v supply n low drift (20ppm/c max) 2.048v or 4.096v internal reference n 1.8v to 2.5v i/o voltages n cmos or lvds spi-compatible serial i/o n power dissipation 20mw/ch (typ) n small 52-lead (7mm 8mm) qfn package n high speed data acquisition systems n communications n remote data acquisition n imaging n optical networking n automotive n multiphase motor control all registered trademarks and trademarks are the property of their respective owners. br r rbrr true differential inputs no configuration required in + , in ? r lt c2320-12 rev b 0.3 0.4 0.5 0.6 0.7 ?140 ?120 ?100 ?80 ?60 snr = 78.4db ?40 ?20 0 amplitude (dbfs) 232012 ta01b 1f 10f 10f 10f 10f thd = ?90.9db 10f 1f s/h a in1 + a in1 ? s/h a in2 + a in2 ? mux 12-bit + sign sar adc sinad = 78.2db 12-bit + sign sar adc 12-bit + sign sar adc 12-bit + sign sar adc s/h a in3 + a in3 ? s/h a in4 + a in4 ? mux sfdr = 95.2db s/h a in5 + a in5 ? s/h a in6 + a in6 ? mux s/h a in7 + a in7 ? frequency (mhz) s/h a in8 + a in8 ? mux ov dd ref gnd gnd refout1 v dd 0 1.8v to 2.5v 3.3v or 5v cmos /lvds sdr/ddr refbufen sdo1 sdo2 sdo3 sdo4 sdo5 0.1 sdo6 sdo7 sdo8 clkout sck cnv sample clock refout2 refout3 0.2 refout4 eight simultaneous sampling channels LTC2320-12 232012 ta01a
2 for more information www.analog.com pin configuration absolute maximum ratings supply voltage (v dd ) .................................................. 6v su pply voltage (ov dd ) ................................................ 3v an alog input voltage a in + , a in C (note 3) ................... C 0. 3v to (v dd + 0.3v ) r efout1,2,3,4 ........................ .C 0.3v to (v dd + 0.3v ) cnv ........................................ C 0.3v to (ov dd + 0.3v ) digital input voltage (note 3) .......................... (g nd C 0.3v ) to (ov dd + 0.3v ) digital output voltage (note 3) .......................... (g nd C 0.3v ) to (ov dd + 0.3v ) operating temperature range lt c23 20 c ................................................ 0c to 70 c lt c23 20 i ............................................. C 40 c to 85 c lt c23 20 h .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) b r b r r r clkouten b b r rb r sdrr cnv cmos order information lead free finish tape and reel part marking* package description temperature range ltc2320cukg-12#pbf ltc2320cukg-12#trpbf ltc2320ukg-12 52-lead (7mm 8mm) plastic qfn 0c to 70c ltc2320iukg-12#pbf ltc2320iukg-12#trpbf ltc2320ukg-12 52-lead (7mm 8mm) plastic qfn C40c to 85c ltc2320hukg-12#pbf ltc2320hukg-12#trpbf ltc2320ukg-12 52-lead (7mm 8mm) plastic qfn C40c to 125c consult adi marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http://www.linear.com/product/LTC2320-12#orderinfo lt c2320-12 rev b
3 for more information www.analog.com electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). symbol parameter conditions min typ max units v in + absolute input range (a in + to a in C ) (note 5) l 0 v dd v v in C absolute input range (a in + to a in C ) (note 5) l 0 v dd v v in + C v in C input differential voltage range v in = v in + C v in C l Crefout1,2,3,4 refout1,2,3,4 v v cm common mode input range v cm = (v in + C v in C )/2 l 0 v dd v i in analog input dc leakage current l C1 1 a c in analog input capacitance 10 pf cmrr input common mode rejection ratio f in = 500khz 102 db v ihcnv cnv high level input voltage l 1.5 v v ilcnv cnv low level input voltage l 0.5 v i incnv cnv input current l C10 10 a converter characteristics symbol parameter conditions min typ max units resolution l 12 bits no missing codes l 12 bits transition noise 0.2 lsb rms inl integral linearity error (note 6) l C1 0.25 1 lsb dnl differential linearity error l C0.99 0.4 0.99 lsb bze bipolar zero-scale error (note 7) l C1.5 0 1.5 lsb bipolar zero-scale error drift 0.005 lsb/c fse bipolar full-scale error v refout1,2,3,4 = 4.096v (refbufen grounded) (note 7) l C3 0 3 lsb bipolar full-scale error drift v refout1,2,3,4 = 4.096v (refbufen grounded) 15 ppm/c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). dynamic accuracy symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 500khz, v refout1,2,3,4 = 4.096v, internal reference l 74 77 db f in = 500khz, v refout1,2,3,4 = 5v, external reference 77 db snr signal-to-noise ratio f in = 500khz, v refout1,2,3,4 = 4.096v, internal reference l 75 77 db f in = 500khz, v refout1,2,3,4 = 5v, external reference 77.5 db thd total harmonic distortion f in = 500khz, v refout1,2,3,4 = 4.096v, internal reference l C90 C76 db f in = 500khz, v refout1,2,3,4 = 5v, external reference C91 db sfdr spurious free dynamic range f in = 500khz, v refout1,2,3,4 = 4.096v, internal reference l 76 93 db f in = 500khz, v refout1,2,3,4 = 5v, external reference 93 db C3db input bandwidth 55 mhz aperture delay 500 ps aperture delay matching 500 ps aperture jitter 1 ps rms transient response full-scale step 30 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs (notes 4, 8). lt c2320-12 rev b
4 for more information www.analog.com internal reference characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). digital inputs and digital outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). symbol parameter conditions min typ max units v refout1,2,3,4 internal reference output voltage 4.75v < v dd < 5.25v 3.13v < v dd < 3.47v l l 4.078 2.034 4.096 2.048 4.115 2.064 v v v ref temperature coefficient (note 14) l 3 20 ppm/c refout1,2,3,4 output impedance 0.25 ? v refout1,2,3,4 line regulation 4.75v < v dd < 5.25v 0.3 mv/v i refout1,2,3,4 external reference current refbufen = 0v refout1,2,3,4 = 4.096v refout1,2,3,4 = 2.048v (notes 9, 10) 385 204 a a symbol parameter conditions min typ max units cmos digital inputs and outputs cmos/l vds = gnd v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance l 5 pf v oh high level output voltage i o = C500a l ov dd C 0.2 v v ol low level output voltage i o = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v l C10 ma i sink output sink current v out = ov dd l 10 ma lvds digital inputs and outputs cmos/l vds = ov dd v id lvds differential input voltage 100 differential termination ov dd = 2.5v l 240 600 mv v is lvds common mode input voltage 100 differential termination ov dd = 2.5v l 1 1.45 v v od lvds differential output voltage 100 differential termination ov dd = 2.5v l 220 350 600 mv v os lvds common mode output voltage 100 differential termination ov dd = 2.5v l 0.85 1.2 1.4 v v od_lp low power lvds differential output voltage 100 differential termination ov dd = 2.5v l 100 200 350 mv v os_lp low power lvds common mode output voltage 100 differential termination ov dd = 2.5v l 0.85 1.2 1.4 v lt c2320-12 rev b
5 for more information www.analog.com symbol parameter conditions min typ max units f smpl maximum sampling frequency l 1.5 msps t cyc time between conversions (note 11) t cyc = t cnvh + t conv + t readout l 0.667 1000 s t conv conversion time l 450 ns t cnvh cnv high time l 30 ns t acquisition sampling aperture (note 11) t acquisition = t cyc C t conv 215 ns t wake refout1,2,3,4 wake-up time c refout1,2,3,4 = 10f 50 ms cmos i/o mode, sdr cmos /lvds = gnd, sdr/ ddr = gnd t sck sck period (note 13) l 9.1 ns t sckh sck high time l 4.1 ns t sckl sck low time l 4.1 ns t hsdo_sdr sdo data remains valid delay from clkout c l = 5pf (note 12) l 0 1.5 ns t dsckclkout sck to clkout delay (note 12) l 2 4.5 ns power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). symbol parameter conditions min typ max units v dd supply voltage 5v operation 3.3v operation l l 4.75 3.13 5.25 3.47 v v iv dd supply current 1.5msps sample rate (in + = in C = 0v) l 31 38 ma cmos i/o mode cmos /lvds = gnd ov dd supply voltage l 1.71 2.63 v i ovdd supply current 1.5msps sample rate (c l = 5pf) l 4.4 7 ma i nap nap mode current conversion done (i vdd ) l 5.3 6.2 ma i sleep sleep mode current sleep mode (i vdd + i ovdd ) l 20 110 a p d_3.3v power dissipation v dd = 3.3v, 1.5msps sample rate nap mode sleep mode l l l 102 18 20 130 26.6 355 mw mw w p d_5v power dissipation v dd = 5v, 1.5msps sample rate nap mode sleep mode l l l 162 27 30 208 31.2 525 mw mw w l vds i/o mode cmos /lvds = ov dd , ov dd = 2.5v ov dd supply voltage l 2.37 2.63 v i ovdd supply current 1.5msps sample rate (c l = 5pf, r l = 100) l 26 34 ma i nap nap mode current conversion done (i vdd ) l 5.3 6.2 ma i sleep sleep mode current sleep mode (i vdd + i ovdd ) l 20 110 a p d_3.3v power dissipation v dd = 3.3v, 1.5msps sample rate nap mode sleep mode l l l 151 52 80 196 60 355 mw mw w p d_5v power dissipation v dd = 5v, 1.5msps sample rate nap mode sleep mode l l l 214 51 30 275 68.5 525 mw mw w adc timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). lt c2320-12 rev b
6 for more information www.analog.com note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground, or above v dd or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground, or above v dd or ov dd , without latch-up. note 4 : v dd = 5v, ov dd = 2.5v, refout1,2,3,4 = 4.096v, f smpl = 1.5mhz. note 5: recommended operating conditions. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar zero error is the offset voltage measured from C0.5lsb when the output code flickers between 0000 0000 0000 0 and 1111 1111 1111 1. full-scale bipolar error is the worst-case of Cfs or +fs untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. note 8: all specifications in db are referred to a full-scale 4.096v input with ref = 4.096v. note 9: when refout1,2,3,4 is overdriven, the internal reference buffer must be turned off by setting refbufen = 0v. note 10: f smpl = 1.5mhz, i refout1,2,3,4 varies proportionally with sample rate. note 11: guaranteed by design, not subject to test. note 12: parameter tested and guaranteed at ov dd = 1.71v and ov dd = 2.5v. note 13: t sck of 9.1ns allows a shift clock frequency up to 105mhz for rising edge capture. note 14: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. note 15: cnv is driven from a low jitter digital source, typically at ov dd logic levels. adc timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). symbol parameter conditions min typ max units t dcnvsdoz bus relinquish time after cnv (note 11) l 3 ns t dcnvsdov sdo valid delay from cnv (note 11) l 3 ns t dsckhcnvh sck delay time to cnv (note 11) l 0 ns cmos i/o mode, ddr cmos /lvds = gnd, sdr/ ddr = ov dd t sck sck period l 18.2 ns t sckh sck high time l 8.2 ns t sckl sck low time l 8.2 ns t hsdo_ddr sdo data remains valid delay from clkout c l = 5pf (note 12) l 0 1.5 ns t dsckclkout sck to clkout delay (note 12) l 2 4.5 ns t dcnvsdoz bus relinquish time after cnv (note 11) l 3 ns t dcnvsdov sdo valid delay from cnv (note 11) l 3 ns t dsckhcnvh sck delay time to cnv (note 11) l 0 ns lvds i/o mode, sdr cmos /lvds = ov dd , sdr/ddr = gnd t sck sck period l 3.3 ns t sckh sck high time l 1.5 ns t sckl sck low time l 1.5 ns t hsdo_sdr sdo data remains valid delay from clkout c l = 5pf ov dd = 2.5v l 0 1.5 ns t dsckclkout sck to clkout delay ov dd = 2.5v l 2 4 ns t dsckhcnvh sck delay time to cnv (note 11) l 0 ns lvds i/o mode, ddr cmos /lvds = ov dd , sdr/ddr = ov dd t sck sck period l 6.6 ns t sckh sck high time l 3 ns t sckl sck low time l 3 ns t hsdo_ddr sdo data remains valid delay from clkout c l = 5pf ov dd = 2.5v l 0 1.5 ns t dsckclkout sck to clkout delay ov dd = 2.5v l 2 4 ns t dsckhcnvh sck delay time to cnv (note 11) l 0 ns lt c2320-12 rev b
7 for more information www.analog.com figure?1. voltage levels for timing specifications 0.8 ? ov dd 0.2 ? ov dd 50% 50% 232012 f01 0.2 ? ov dd 0.8 ? ov dd 0.2 ? ov dd 0.8 ? ov dd t delay t width t delay adc timing characteristics lt c2320-12 rev b
8 for more information www.analog.com typical performance characteristics thd, harmonics vs input common mode snr, sinad vs reference voltage, f in = 500khz 32k point fft, imd, f smpl = 1.5msps , a in + = 490khz, a in C = 510khz 32k point fft, f smpl = 1.5msps, f in = 500khz snr, sinad vs input frequency (1khz to 750khz) thd, harmonics vs input frequency (1khz to 750khz) integral nonlinearity vs output code differential nonlinearity vs output code dc histogram t a = 25c, v dd = 5v, ov dd = 2.5v, refout1,2,3,4 = 4.096v, f smpl = 1.5msps, unless otherwise noted. lt c2320-12 rev b ?0.50 frequency (mhz) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ?0.25 ?120 ?116 ?112 ?108 ?104 ?100 ?96 ?92 ?88 ?84 0 ?80 thd, harmonics level (dbfs) 232012 g06 thd hd3 hd2 f in = 500khz input common mode (v) 1.5 1.7 0.25 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 ?120 ?116 0.50 ?112 ?108 ?104 ?100 ?96 ?92 ?88 ?84 ?80 thd, harmonics level (dbfs) 0.75 mode 232012 g07 snr sinad f in = 500khz v refout (v) 0.5 1 1.5 2 1.00 2.5 3 3.5 4 4.5 5 64 66 68 70 inl error (lsb) 72 74 76 78 80 snr, sinad level (dbfs) f in = 500khz 232012 g08 thd = 87db v cm = 20khz, 4v p-p 232012 g01 frequency (mhz) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 ?140 right click in graph area for menu ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) in in 232012 g09 output code double click in graph area for data setup output code ?4096 ?2048 0 2048 4096 ?1.0 ?0.5 0 ?4096 0.5 1.0 dnl error (lsb) 232012 g02 code ?2 ?1 0 1 2 ?2048 0 17500 35000 52500 70000 counts dc histogram 232012 g03 snr = 78.4db thd = ?90.9db 0 sinad = 78.2db sfdr = 95.2db frequency (mhz) 0 0.1 0.2 0.3 0.4 0.5 0.6 2048 0.7 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 4096 smpl in 232012 g04 snr sinad frequency (mhz) 0 0.1 0.2 0.3 0.4 ?1.00 0.5 0.6 0.7 0.8 75.0 75.5 76.0 76.5 77.0 77.5 ?0.75 78.0 78.5 79.0 79.5 80.0 snr, sinad level (dbfs) 232012 g05 thd hd3 hd2
9 for more information www.analog.com typical performance characteristics step response (fine settling) external reference supply current vs sample frequency ref output vs temperature offset error vs temperature supply current vs sample frequency ov dd current vs sck frequency, c load = 10pf cmrr vs input frequency crosstalk vs input frequency step response (large signal settling) t a = 25c, v dd = 5v, ov dd = 2.5v, refout1,2,3,4 = 4.096v, f smpl = 1.5msps, unless otherwise noted. lt c2320-12 rev b 100 ?35 ?15 5 25 45 65 85 105 125 ?3.00 105 ?2.50 ?2.00 ?1.50 ?1.00 ?0.50 0 0.50 1.00 ref output error (mv) ref output vs temperature 110 232012 g15 temperature (c) ?55 ?35 ?15 5 25 45 65 85 115 105 125 ?0.250 ?0.125 0 0.125 0.250 lsb offset error vs temperature 232012 g16 120 v dd = 5v v dd = 3.3v sample frequency (msps) 0 0.3 0.6 0.9 1.2 1.5 19 cmrr (db) 21 23 25 27 29 31 33 supply current (ma) vs sample frequency 232012 g17 cmrr vs input frequency lvds (4 lanes) cmos (2.5v, 8 lanes) low power lvds (4 lanes) cmos(1.8v, 8 lanes) full scale sinusoidal input sck frequency (mhz) 0 50 100 150 232012 g10 200 250 300 0 1 2 3 4 5 6 4.096v range 7 8 12 14 16 18 20 22 24 26 in+ = 1.5mhz square wave 28 30 32 ov dd current cmos (ma) ov dd current lvds (ma) c load = 10pf, 232012 g18 frequency (khz) 0 100 v cm = 4v p-p in? = 0v 200 300 400 500 600 700 ?100 ?99 ?98 ?97 settling time (ns) ?96 ?95 ?94 ?93 ?92 ?91 ?90 crosstalk (db) 232012 g11 ?20 ?10 0 10 20 30 40 50 frequency (khz) 60 70 80 90 ?1024 0 1024 2048 3072 4096 0 output code (lsb) 232012 g12 in+ = 1.5mhz square wave in? = 0v 4.096v range settling time (ns) ?20 ?10 0 10 500 20 30 40 50 60 70 80 90 ?100 ?80 1000 ?60 ?40 ?20 0 20 40 60 80 100 deviation from final value (lsb) 1500 (fine settling) 232012 g13 v refout1,2,3,4 = 4.096v v refout1,2,3,4 = 2.048v refbufen = 0v (ext ref buf overdriving ref buf) sample frequency (msps) 0 0.3 90 0.6 0.9 1.2 1.5 0 50 100 150 200 250 95 300 350 400 supply current (ua) current vs sample frequency 232012 g14 v dd = 3.3v v dd = 5v temperature (c) ?55
10 for more information www.analog.com pin functions pins that are the same for all digital i/o modes. a in6 + , a in6 C (pins 2, 1): analog differential input pins. full-scale range (a in6 + C a in6 C ) is refout3 voltage. these pins can be driven from v dd to gnd. gnd (pins 3, 7, 12, 18, 26, 32, 38, 46, 49): ground. these pins and exposed pad (pin 53) must be tied directly to a solid ground plane. a in5 + , a in5 C (pins 5, 4): analog differential input pins. full-scale range (a in5 + C a in5 C ) is refout3 voltage. these pins can be driven from v dd to gnd. refout3 (pin 6): reference buffer 3 output. an onboard buffer nominally outputs 4.096v to this pin. this pin is referred to gnd and should be decoupled closely to the pin with a 10f (x5r, 0805 size) ceramic capacitor. the internal buffer driving this pin may be disabled by ground - ing the refbufen pin. if the buffer is disabled, an external reference may drive this pin in the range of 1.25v to 5v. ref (pin 8) : common 4.096v reference output. decouple to gnd with a 1f low esr ceramic capacitor. may be overdriven with a single external reference to establish a common reference for adc cores 1 through 4. refout2 (pin 9): reference buffer 2 output. an onboard buffer nominally outputs 4.096v to this pin. this pin is referred to gnd and should be decoupled closely to the pin with a 10f (x5r, 0805 size) ceramic capacitor. the internal buffer driving this pin may be disabled by ground - ing the refbufen pin. if the buffer is disabled, an external reference may drive this pin in the range of 1.25v to 5v. a in4 + , a in4 C (pins 11, 10): analog differential input pins. full-scale range (a in4 + C a in4 C ) is refout2 voltage. these pins can be driven from v dd to gnd. a in3 + , a in3 C (pins 14, 13): analog differential input pins. full-scale range (a in3 + C a in3 C ) is refout2 voltage. these pins can be driven from v dd to gnd. v dd (pins 15, 21, 44, 52): power supply. bypass v dd to gnd with a 10f ceramic capacitor and a 0.1f ceramic capacitor close to the part. the v dd pins should be shorted together and driven from the same supply. a in2 + , a in2 C (pins 17, 16): analog differential input pins. full-scale range (a in2 + C a in2 C ) is refout1 voltage. these pins can be driven from v dd to gnd. a in1 + , a in1 C (pins 20, 19): analog differential input pins. full-scale range (a in1 + C a in1 C ) is refout1 voltage. these pins can be driven from v dd to gnd. refout1 (pin 22): reference buffer 1 output. an onboard buffer nominally outputs 4.096v to this pin. this pin is referred to gnd and should be decoupled closely to the pin with a 10f (x5r, 0805 size) ceramic capacitor. the internal buffer driving this pin may be disabled by ground - ing the refbufen pin. if the buffer is disabled, an external reference may drive this pin in the range of 1.25v to 5v. sdr /ddr (pin 23): double data rate input. controls the frequency of sck and clkout. tie to gnd for the falling edge of sck to shift each serial data output (single data rate, sdr). tie to ov dd to shift serial data output on each edge of sck (double data rate, ddr). clkout will be a delayed version of sck for both pin states. cnv (pin 24): convert input. this pin, when high, defines the acquisition phase. when this pin is driven low, the conversion phase is initiated and output data is clocked out. this input must be driven at ov dd levels with a low jitter pulse. this pin is unaffected by the cmos /lvds pin. cmos/ lvds (pin 25): i/o mode select. ground this pin to enable cmos mode, tie to ov dd to enable lvds mode. float this pin to enable low power lvds mode. ov dd (pins 31, 37): i/o interface digital power. the range of ov dd is 1.71v to 2.63v. this supply is nominally set to the same supply as the host interface (cmos : 1.8v or 2.5v , lvds : 2.5v). bypass ov dd to gnd (pins 32 and 38) with 0.1f capacitors. lt c2320-12 rev b
11 for more information www.analog.com pin functions refbufen (pin 43): reference buffer output enable. tie to v dd when using the internal reference. tie to ground to disable the internal refout1C4 buffers for use with external voltage references. this pin has a 500k internal pull-up to v dd . refout4 (pin 45): reference buffer 4 output. an onboard buffer nominally outputs 4.096v to this pin. this pin is referred to gnd and should be decoupled closely to the pin with a 10f (x5r, 0805 size) ceramic capacitor. the internal buffer driving this pin may be disabled by ground - ing the refbufen pin. if the buffer is disabled, an external reference may drive this pin in the range of 1.25v to 5v. a in8 + , a in8 C (pins 48, 47): analog differential input pins. full-scale range (a in8 + C a in8 C ) is refout4 voltage. these pins can be driven from v dd to gnd. a in7 + , a in7 C (pins 51, 50): analog differential input pins. full-scale range (a in7 + C a in7 C ) is refout4 voltage. these pins can be driven from v dd to gnd. exposed pad (pin 53): ground. solder this pad to ground. cmos data output option ( cmos /lvds = low) sdo1 (pin 27): cmos serial data output for adc chan - nel 1. the conversion result is shifted msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 13 sck edges are required for 13-bit conver - sion data to be read from sdo1 in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch2, ch3, ch4, ch5, ch6, ch7, ch8). sdo2 (pin 28): cmos serial data output for adc chan - nel 2. the conversion result is shifted msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 13 sck edges are required for 13-bit conver - sion data to be read from sdo2 in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch3, ch4, ch5, ch6, ch7, ch8, ch1). sdo3 (pin 29): cmos serial data output for adc chan - nel 3. the conversion result is shifted msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 13 sck edges are required for 13-bit conver - sion data to be read from sdo3 in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch4, ch5, ch6, ch7, ch8, ch1, ch2). sdo4 (pin 30): cmos serial data output for adc chan - nel 4. the conversion result is shifted msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 13 sck edges are required for 13-bit conver - sion data to be read from sdo4 in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch5, ch6, ch7, ch8, ch1, ch2, ch3). clkout (pin 33): serial data clock output. clkout provides a skew-matched clock to latch the sdo output at the receiver (fpga). the logic level is determined by ov dd . this pin echoes the input at sck with a small delay. clkouten (pin 34): clkout can be disabled by tying pin 34 to ov dd for a small power savings. if clkout is used, ground this pin. sdo5 (pin 35): cmos serial data output for adc chan - nel 5. the conversion result is shifted msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 13 sck edges are required for 13-bit conver - sion data to be read from sdo5 in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch6, ch7, ch8, ch1, ch2, ch3, ch4). sdo6 (pin 36): cmos serial data output for adc chan - nel 6. the conversion result is shifted msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 13 sck edges are required for 13-bit conver - sion data to be read from sdo6 in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch7, ch8, ch1, ch2, ch3, ch4, ch5). lt c2320-12 rev b
12 for more information www.analog.com sdo7 (pin 39): cmos serial data output for adc chan - nel 7. the conversion result is shifted msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 13 sck edges are required for 13-bit conver - sion data to be read from sdo7 in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch8, ch1, ch2, ch3, ch4, ch5, ch6). sdo8 (pin 40): cmos serial data output for adc chan - nel 8. the conversion result is shifted msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 13 sck edges are required for 13-bit conver - sion data to be read from sdo8 in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch1, ch2, ch3, ch4, ch5, ch6, ch7). sck (pin 41): serial data clock input. the falling edge of this clock shifts the conversion result msb first onto the sdo pins in sdr mode (ddr = low). in ddr mode (sdr/ddr = high) each edge of this clock shifts the conversion result msb first onto the sdo pins. the logic level is determined by ov dd . dnc (pin 42): in cmos mode do not connect this pin. lvds data output option ( cmos /lvds = high or float) sdoa + , sdoa C (pins 27, 28): lvds serial data output for adc channels 1 and 2. the conversion result is shifted ch1 msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 32 sck edges are required for 13- bit conversion data to be read from a in1 and a in2 on sdoa in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch3, ch4, ch5, ch6, ch7, c h8).terminate with a 100? resistor at the receiver (fpga). sdob + , sdob C (pins 29, 30): lvds serial data output for adc channels 3 and 4. the conversion result is shifted ch3 msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 32 sck edges are required for 13- bit conversion data to be read from a in3 and a in4 on sdob in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch5, ch6, ch7, ch8, ch1, c h2).terminate with a 100? resistor at the receiver (fpga). clkout + , clkout C (pins 33, 34): serial data clock output. clkout provides a skew-matched clock to latch the sdo output at the receiver. these pins echo the input at sck with a small delay. these pins must be dif - ferentially terminated by an external 100 resistor at the receiver?(fpga). sdoc + , sdoc C (pins 35, 36): lvds serial data output for adc channels 5 and 6. the conversion result is shifted ch5 msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 32 sck edges are required for 13- bit conversion data to be read from a in5 and a in6 on sdoa in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch7, ch8, ch1, ch2, ch3, c h4).terminate with a 100? resistor at the receiver (fpga). sdod + , sdod C (pins 39, 40): lvds serial data output for adc channels 7 and 8. the conversion result is shifted ch7 msb first on each falling edge of sck in sdr mode and each sck edge in ddr mode. 32 sck edges are re - quired for 13-bit conversion data to be read from a in7 and a in8 on sdoa in sdr mode, 13 sck edges in ddr mode. supplying more clocks will yield data from subsequent channels (ch1, ch2, ch3, ch4, ch5, c h6).terminate with a 100? resistor at the receiver (fpga). sck + , sck C (pins 41, 42): serial data clock input. the falling edge of this clock shifts the conversion result msb first onto the sdo pins in sdr mode ( sdr /ddr = low). in ddr mode (sdr/ddr = high) each edge of this clock shifts the conversion result msb first onto the sdo pins. these pins must be differentially terminated by an external 100 resistor at the receiver (adc). pin functions lt c2320-12 rev b
13 for more information www.analog.com functional block diagram 27 28 22 cmos i/o sdo1 sdo2 20 24 19 a in1 + ref a in1 ? cnv v dd (15, 21, 44, 52) ref 1 41 42 cmos receivers output clock driver + ? 17 16 a in2 + a in2 ? + ? s/h s/h 12-bit + sign sar adc 29 30 33 34 23 9 cmos i/o sdo3 sdo4 14 13 a in3 + a in3 ? ref 1 + ? 11 10 a in4 + a in4 ? + ? s/h s/h 12-bit + sign sar adc 35 36 6 cmos i/o sdo6 sdo6 5 4 a in5 + dnc sck a in5 ? ref 1 + ? 2 1 a in6 + a in6 ? + ? s/h s/h 12-bit + sign sar adc 39 40 43 25 45 cmos i/o sdo7 sdo8 refout4 cmos/lvds 51 50 a in7 + a in7 ? ref 1 + ? 48 47 8 a in8 + a in8 ? + ? s/h s/h 12-bit + sign sar adc sdr/ddr refout3 1.7 3.4 1.2v int ref refbufen ov dd (31, 37) clkouten clkout refout2 refout1 250a gnd (3, 7, 12, 18, 26, 32, 38, 46, 49, 53) 232012 bda mux mux mux mux cmos io mode lt c2320-12 rev b
14 for more information www.analog.com 27 28 22 lvds i/o sdoa + sdoa ? 20 24 19 a in1 + ref a in1 ? cnv v dd (15, 21, 44, 52) ref 1 41 42 lvds receivers output clock driver + ? 17 16 a in2 + a in2 ? + ? s/h s/h 12-bit + sign sar adc 29 30 33 34 23 9 lvds i/o sdob + sdob ? 14 13 a in3 + a in3 ? ref 1 + ? 11 10 a in4 + a in4 ? + ? s/h s/h 12-bit + sign sar adc 35 36 6 lvds i/o sdoc + sdoc ? 5 4 a in5 + sck ? sck + a in5 ? ref 1 + ? 2 1 a in6 + a in6 ? + ? s/h s/h 12-bit + sign sar adc 39 40 43 25 45 lvds i/o sdod + sdod ? refout4 cmos/lvds 51 50 a in7 + a in7 ? ref 1 + ? 48 47 8 a in8 + a in8 ? + ? s/h s/h 12-bit + sign sar adc sdr/ddr refout3 1.7 3.4 1.2v int ref refbufen ov dd (31, 37) clkout ? clkout + refout2 refout1 250a gnd (3, 7, 12, 18, 26, 32, 38, 46, 49, 53) 232012 bdb mux mux mux mux lvds io mode functional block diagram lt c2320-12 rev b
15 for more information www.analog.com timing diagram sdr mode, cmos (reading 1 channel per sdo) ddr mode, cmos (reading 1 channel per sdo) lt c2320-12 rev b acquire 12 13 14 15 16 sample n+1 sdo8 channel 8 conversion n channel 1 convert conversion n hi-z hi-z 232012 td02 hi-z dont care d12 d11 d10 d9 sample n d8 d7 d6 d5 d4 d3 d2 d1 d0 0 channel 1 d12 hi-z 0 0 hi-z dont care d12 d11 d10 d9 conversion n d8 d7 d6 d5 d4 d3 d2 d1 d0 0 channel 2 d12 hi-z 0 0 conversion n d12 d11 d10 cnv d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sck 0 d12 3 4 5 6 7 8 9 10 sdo1 11 12 13 14 15 16 sample n+1 sdo8 channel 8 conversion n clkout channel 1 conversion n hi-z hi-z hi-z 232012 td01 0 0 hi-z dont care hi-z d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 1 d2 d1 d0 0 d12 hi-z 0 0 cnv sck 2 sdo1 clkout 1 2 acquire convert sample n channel 1 conversion n channel 2 dont care conversion n 3 4 5 6 7 8 9 10 11
16 for more information www.analog.com sdr mode, lvds (reading 2 channels per sdo pair) ddr mode, lvds (reading 2 channels per sdo pair) timing diagram lt c2320-12 rev b convert d3 d2 d1 d0 d12 d12 d11 d10 d9 d8 sample n d7 d6 d5 d4 d3 d2 d1 d0 0 0 channel 1 0 0 0 0 cnv sck sdoa clkout 1 2 conversion n acquire convert sample n channel 1 conversion n channel 3 conversion n 3 4 5 channel 3 6 7 8 9 10 11 12 13 14 15 conversion n 16 sample n+1 sdod channel 7 conversion n channel 1 conversion n channel 2 conversion n channel 8 d12 conversion n 17 18 19 20 21 22 23 24 25 d11 26 27 28 29 30 31 32 232012 td04 dont care d12 d10 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d9 d1 d0 d12 d12 d11 d10 d9 d8 d7 d6 cnv d8 d5 d4 d3 d2 d1 d0 0 0 0 0 d7 0 0 dont care d12 d11 d10 d9 d8 d7 d6 d6 d5 d4 d3 d2 d1 d0 d12 d12 d11 d10 d5 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d4 0 0 0 0 0 0 d3 d2 d1 d0 d12 sck 3 4 5 6 7 8 9 10 11 12 sdoa 13 14 15 16 sample n+1 sdod channel 7 conversion n channel 1 conversion n clkout d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 1 d2 d1 d0 channel 2 conversion n channel 8 conversion n 17 18 19 2 20 21 22 23 24 25 26 27 28 29 dont care 30 31 32 232012 td03 0 0 0 0 0 0 acquire dont care d12 d11 d10 d9 d8 d7 d6 d5 d4
17 for more information www.analog.com applications information overview the ltc2320 -12 is a low noise, high speed 12-bit succes - sive approximation register (sar) adc with differential inputs and a wide input common mode range. operating from a single 3.3v or 5v supply, the LTC2320-12 has a 4v p-p or 8v p-p differential input range, making it ideal for applications which require a wide dynamic range. the LTC2320-12 achieves 0.25lsb inl typical, no missing codes at 12 bits and 77db snr. the ltc2320 -12 has an onboard reference buffer and low drift (20ppm/c max) 4.096v temperature-compensated reference. the LTC2320-12 also has a high speed spi- compatible serial interface that supports cmos or lvds. the fast 1.5msps per channel throughput with no latency makes the LTC2320-12 ideally suited for a wide variety of high speed applications. the LTC2320-12 dissipates only 20mw per channel. nap and sleep modes are also provided to reduce the power consumption of the LTC2320-12 dur - ing inactive periods for further power savings. conver ter opera tion the ltc2320 -12 operates in two phases. during the ac - quisition phase, the sample capacitor is connected to the analog input pins a in + and a in C to sample the differential analog input voltage, as shown in figure?3. a falling edge on the cnv pin initiates a conversion. during the conversion phase, the 12- bit cdac is sequenced through a successive approximation algorithm effectively comparing the sampled input with binary-weighted fractions of the reference volt - age (e.g., v refout /2, v refout /4 v refout /32768) using a differential comparator. at the end of conversion, a cdac output approximates the sampled analog input. the adc control logic then prepares the 12-bit digital output code for serial transfer. transfer function the ltc2320 -12 digitizes the full-scale voltage of 2 ? refout into 2 13 levels, resulting in an lsb size of 1mv with refbuf = 4.096v . the ideal transfer function is shown in figure?2. the output data is in 2 s complement format. when driven by fully differential inputs, the transfer func - tion spans 2 13 codes. when driven by pseudo-differential inputs, the transfer function spans 2 12 codes. figure?2. LTC2320-12 transfer function figure?3. the equivalent circuit for the differential analog input of the LTC2320-12 r on 15 r on 15 bias voltage 232012 f03 c in 10pf v dd c in 10pf v dd a in ? a in + input voltage (v) ?refout refout ? 1lsb output code (two?s complement) 232012 f02 0 1111 1111 1111 0 1111 1111 1110 1 1111 1111 1111 1 0000 0000 0000 1 0000 0000 0001 0 0000 0000 0000 0 0000 0000 0001 ?1 lsb 1lsb = 0 1 lsb 2 ? refout 8192 table 1. code ranges for the analog input operational modes mode span (v in + C v in C ) min code max code fully differential Crefout to +refout 1 0000 0000 0000 0 1111 1111 1111 pseudo-differential bipolar C-refout/2 to +refout/2 1 1000 0000 0000 0 0111 1111 1111 pseudo-differential unipolar 0 to refout 0 0000 0000 0000 0 1111 1111 1111 lt c2320-12 rev b
18 for more information www.analog.com applications information analog input the differential inputs of the LTC2320-12 provide great flexibility to convert a wide variety of analog signals with no configuration required. the LTC2320-12 digitizes the difference voltage between the a in + and a in C pins while supporting a wide common mode input range. the analog input signals can have an arbitrary relationship to each other, provided that they remain between v dd and gnd. the ltc2320 -12 can also digitize more limited classes of analog input signals such as pseudo-differential unipolar/ bipolar and fully differential with no configuration required. the analog inputs of the ltc2320 -12 can be modeled by the equivalent circuit shown in figure?3. the back- to-back diodes at the inputs form clamps that provide esd protection. in the acquisition phase, 10pf (c in ) from the sampling capacitor in series with approximately 15 ?( r on ) from the on-resistance of the sampling switch is connected to the input. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the adc sampler. the inputs of the adc core draw a small current spike while charging the c in capacitors during acquisition. single-ended signals single-ended signals can be directly digitized by the ltc2320 -12. these signals should be sensed pseudo- differentially for improved common mode rejection. by connecting the reference signal (e.g., ground sense) of the main analog signal to the other a in pin, any noise or disturbance common to the two signals will be rejected by the high cmrr of the adc. the ltc2320 -12 flexibility handles both pseudo-differential unipolar and bipolar signals, with no configuration required. the wide common mode input range relaxes the accuracy requirements of any signal conditioning circuits prior to the analog inputs. pseudo-differential bipolar input range the pseudo-differential bipolar configuration represents driving one of the analog inputs at a fixed voltage, typically v ref /2, and applying a signal to the other a in pin. in this case the analog input swings symmetrically around the fixed input yielding bipolar two s complement output codes with an adc span of half of full-scale. this configuration is illustrated in figure?4, and the corresponding transfer function in figure?5. the fixed analog input pin need not be set at v ref /2, but at some point within the v dd rails allowing the alternate input to swing symmetrically around this voltage. if the input signal (a in + C a in C ) swings beyond refout1,2,3,4/2, valid codes will be generated by the adc and must be clamped by the user, if necessary. pseudo-differential unipolar input range the pseudo-differential unipolar configuration represents driving one of the analog inputs at ground and applying a signal to the other a in pin. in this case, the analog input swings between ground and v ref yielding unipolar twos complement output codes with an adc span of half of full-scale. this configuration is illustrated in figure?6, and the corresponding transfer function in figure?7. if the input signal (a in + C a in C ) swings negative, valid codes will be figure?4. pseudo-differential bipolar application circuit 25 25 220pf v ref 0v v ref 0v v ref /2 v ref /2 v ref 10k 10k only channel 1 shown for clarity + ? + ? LTC2320-12 lt1819 232012 f04 sdo1 ref refout1 clkout a in1 ? a in1 + sck to control logic (fpga, cpld, dsp, etc.) 1f 10f 1f lt c2320-12 rev b
19 for more information www.analog.com applications information 25 25 220pf v ref 0v v ref 0v + ? LTC2320-12 lt1818 232012 f06 sdo1 ref refout1 clkout a in1 ? a in1 + sck to control logic (fpga, cpld, dsp, etc.) 1f 10f 232012 f07 ?v ref ?2048 2047 ?4096 4095 v ref dotted regions available but unused a in (a in + ? a in ? ) adc code (2?s complement) ?v ref /2 v ref /2 0 figure?5. pseudo-differential bipolar transfer function 232012 f05 ?v ref ?2048 2047 ?4096 4095 v ref dotted regions available a in (a in + ? a in ? ) adc code (2?s complement) ?v ref /2 v ref /2 0 figure?6. pseudo-differential unipolar application circuit figure?7. pseudo-differential unipolar transfer function lt c2320-12 rev b
20 for more information www.analog.com applications information generated by the adc and must be clamped by the user, if necessary. single-ended-to-differential conversion while single-ended signals can be directly digitized as pre - viously discussed, single-ended to differential conversion cir cuits may also be used when higher dynamic range is desired. by producing a differential signal at the inputs of the LTC2320-12, the signal swing presented to the adc is maximized, thus increasing the achievable snr. the lt ? 1819 high speed dual operational amplifier is recommended for performing single-ended-to-differential conversions, as shown in figure?8. in this case, the first amplifier is configured as a unity-gain buffer and the single-ended input signal directly drives the high imped - ance input of this amplifier. figure?8. single-ended to differential driver v ref 0v v ref 0v v ref 0v v ref /2 + ? + ? 200 200 lt1819 232012 f08 fully-differential inputs to achieve the best distortion performance of the ltc2320 - 12, we recommend driving a fully-differential s ignal through lt1819 amplifiers configured as two unity-gain buffers, as shown in figure? 9. this circuit achieves the full data sheet thd specification of C90db at input frequencies up to 500khz. a fully-differential input signal can span the maximum full-scale of the adc, up to refout1,2,3,4. the common mode input voltage can span the entire supply range up to v dd , limited by the input signal swing. the fully-differential configuration is illustrated in figure?10, with the corresponding transfer function illustrated in figure?11. 25 25 220pf v ref 0v v ref 0v v ref 0v v ref 0v only channel 1 shown for clarity + ? + ? LTC2320-12 lt1819 232012 f10 sdo1 ref refout1 clkout a in1 ? a in1 + sck to control logic (fpga, cpld, dsp, etc.) 1f 10f figure?9. lt1819 buffering a fully-differential signal source v ref 0v v ref 0v v ref 0v v ref 0v + ? + ? lt1819 232012 f09 figure?10. fully-differential application circuit lt c2320-12 rev b
21 for more information www.analog.com applications information input drive circuits a low impedance source can directly drive the high im - pedance inputs of the ltc2320 -12 without gain error. a high impedance sour ce should be buffered to minimize settling time during acquisition and to optimize the dis - tortion performance of the adc. minimizing settling time is important even for dc inputs, because the adc inputs draw a current spike when during acquisition. for best per formance, a buffer amplifier should be used to drive the analog inputs of the LTC2320-12. the amplifier provides low output impedance to minimize gain error and allows for fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the adc inputs, which draw a small current spike during acquisition. input filtering the noise and distortion of the buffer amplifier and signal source must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier input with a low bandwidth filter to minimize noise. the simple 1- pole rc lowpass filter shown in figure?12 is sufficient for many applications. the sampling switch on-resistance (r on ) and the sample capacitor (c in ) form a second lowpass filter that limits the input bandwidth to the adc core to 110mhz. a buffer amplifier with a low noise density must be selected to minimize the degradation of the snr over this bandwidth. figure?12. input signal chain 50 single-ended input signal 232012 f12 bw = 1mhz 3.3nf single-ended to differential driver in + in ? ltc2320 figure?11. fully-differential transfer function 232012 f11 ?v ref v ref a in (a inn + ? a inn ? ) adc code (2?s complement) ?v ref /2 v ref /2 0 ?2048 2047 ?4096 4095 high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. adc reference internal reference the ltc2320 -12 has an on-chip, low noise, low drift?(20ppm/ c max), temperature compensated band - gap reference. it is internally buffered and is available at ref (pin? 8). the reference buffer gains the internal reference voltage to 4.096v for supply voltages v dd = 5v and to 2.048v for v dd = 3.3v . the ref pin also drives the four internal reference buffers with a current limited output? (250a ) so it may be easily overdriven with an external reference in the range of 1.25v to 5v. bypass ref to gnd with a 1f (x5r, 0805 size) ceramic capacitor to compensate the reference buffer and minimize noise. the 1f capacitor should be as close as possible to the LTC2320-12 package to minimize wiring inductance. the voltage on the ref pin must be externally buffered if used for external circuitry. external reference the internal refout1,2,3,4 buffers can also be over - driven from 1.25v to 5v with an external reference at refout1,2,3,4 as shown in figure? 13 (c). t o do so, refbufen must be grounded to disable the ref buffers. a 55k internal resistance loads the refout1,2,3,4 pins when the ref buffers are disabled. to maximize the input lt c2320-12 rev b
22 for more information www.analog.com applications information table 2. table 2. reference configurations and ranges reference configuration v dd refbufen ref pin refout1,2,3,4 pin differential input range pin internal reference with internal buffers 5v 5v 4.096v 4.096v 4.096v 3.3v 3.3v 2.048v 2.048v 2.048v common external reference with internal buffer (ref pin externally overdriven) 5v 5v 1.25v to 5v 1.25v to 3.3v 1.25v to 5v 3.3v 3.3v 1.25v to 5v 1.25v to 3.3v 1.25v to 3.3v external reference with ref buffers disabled 5v 0v 4.096v 1.25v to 5v 1.25v to 5v 3.3v 0v 2.048v 1.25v to 3.3v 1.25v to 3.3v (13a) LTC2320-12 internal reference circuit (13b) LTC2320-12 with a shared external reference circuit (13c) LTC2320-12 with different external reference voltages figure?13. reference connections ltc6655-4.096 5v to 13.2v 0.1f v dd LTC2320-12 gnd 232012 f13b +5v ref refout1 refout2 refout3 refout4 refbufen 10f 10f 10f 10f 10f v in shdn v out_f v out_s 5v to 13.2v 0.1f v dd LTC2320-12 gnd 232012 f13c +5v refout1 ref refout2 refout3 refout4 refbufen 10f ltc6655-4.096 1f v in shdn v out_f v out_s 5v to 13.2v 0.1f 10f ltc6655-2.048 v in shdn v out_f v out_s 5v to 13.2v 0.1f 10f ltc6655-2.5 v in shdn v out_f v out_s 5v to 13.2v 0.1f 10f ltc6655-3 v in shdn v out_f v out_s v dd LTC2320-12 gnd 232012 f13a 3.3v to 5v ref refout1 refout2 refout3 refout4 refbufen 1f 10f 10f 10f 10f lt c2320-12 rev b
23 for more information www.analog.com applications information signal swing and corresponding snr, the ltc6655-5 is recommended when overdriving refout. the ltc6655-5 offers the same small size, accuracy, drift and extended temperature range as the ltc6655-4.096. by using a 5v reference, a higher snr can be achieved. we recommend bypassing the ltc6655-5 with a 10f ceramic capacitor (x5r, 0805 size) close to each of the refout1,2,3,4 pins. if the ref pin voltage is used as a refout refer - ence when refbufen is connected to gnd, it should be buffered externally . internal reference buffer t ransient response the refout1,2,3,4 pins of the LTC2320-12 draw charge (q conv ) from the external bypass capacitors during each conversion cycle. if the internal reference buffer is over - driven, the external reference must provide all of this charge with a dc current equivalent to i ref = q conv /t cyc . thus, the dc current draw of i refout1,2,3,4 depends on the sampling rate and output code. in applications where a burst of samples is taken after idling for long periods, as shown in figure?14 , i refbuf quickly goes from approximately ~75a to a maximum of 500a for refout = 5v at 1.5msps. this step in dc current draw triggers a transient response in the external reference that must be considered since any deviation in the voltage at refout will affect the accuracy of the output code. if an external reference is used to overdrive refout1,2,3,4, the fast settling ltc6655 reference is recommended. cnv 232012 f14 idle period figure?14. cnv waveform showing burst sampling figure?15. transient response of the LTC2320-12 dynamic performance fast fourier transform (fft) techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequen - cies outside the fundamental. the LTC2320-12 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is bandlimited to frequencies from above dc and below half the sampling frequency. figure?16 shows that the LTC2320-12 achieves a typical sinad of 77db at a 1.5mhz sampling rate with a 500khz input. signal-to-noise ratio (snr) the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure?16 shows that the LTC2320-12 achieves a typical snr of 77db at a 1.5mhz sampling rate with a 500khz input. lt c2320-12 rev b 20 30 40 50 60 70 80 90 ?1024 0 4.096v range 1024 2048 3072 4096 output code (lsb) 232012 f15 in+ = 1.5mhz square wave in? = 0v settling time (ns) ?20 ?10 0 10
24 for more information www.analog.com applications information total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20 log v2 2 + v3 2 + v 4 2 + + v n 2 v1 where v1 is the rms amplitude of the fundamental frequency and v2 through v n are the amplitudes of the second through nth harmonics. power considerations the ltc2320 -12 requires two power supplies: the 3.3v to 5v power supply (v dd ), and the digital input/output interface power supply (ov dd ). the flexible ov dd supply allows the ltc2320 -12 to communicate with any digital logic operating between 1.8v and 2.5v . when using lvds i/o, the ov dd supply must be set to 2.5v. power supply sequencing the ltc2320 -12 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2320 - 12 has a power -on-reset (por) circuit that will reset the ltc2320 -12 at initial power-up or whenever the power figure?16. 32k point fft of the LTC2320-12 supply voltage drops below 2v. once the supply voltage re-enters the nominal supply voltage range, the por will reinitialize the adc. no conversions should be initiated until 10ms after a por event to ensure the reinitialization period has ended. any conversions initiated before this time will produce invalid results. timing and control cnv timing the ltc2320 -12 sampling and conversion is controlled by cnv . a rising edge on cnv will start sampling and the falling edge starts the conversion and readout process. the conversion process is timed by the sck input clock. for optimum performance, cnv should be driven by a clean low jitter signal. the typical application at the back of the data sheet illustrates a recommended implementation to reduce the relatively large jitter from an fpga cnv pulse source. note the low jitter input clock times the falling edge of the cnv signal. the rising edge jitter of cnv is much less critical to performance. the typical pulse width of the cnv signal is 30ns with < 1.5ns rise and fall times at a 1.5msps conversion rate. sck serial data clock input in sdr mode (sdr/ddr pin 23 = gnd), the falling edge of this clock shifts the conversion result msb first onto the sdo pins. a 100mhz external clock must be applied at figure?17. power supply current of the LTC2320-12 versus sampling rate lt c2320-12 rev b 0.3 0.4 0.5 0.6 0.7 ?140 ?120 ?100 ?80 ?60 snr = 78.4db ?40 ?20 0 amplitude (dbfs) smpl in 232012 f16 v dd = 5v v dd = 3.3v sample frequency (msps) 0 thd = ?90.9db 0.3 0.6 0.9 1.2 1.5 19 21 23 25 27 sinad = 78.2db 29 31 33 supply current (ma) 232012 f17 sfdr = 95.2db frequency (mhz) 0 0.1 0.2
25 for more information www.analog.com applications information the sck pin to achieve 1.5msps throughput using all eight sdo outputs. in ddr mode (sdr/ddr pin 23 = ov dd ), each input edge of sck shifts the conversion result msb first onto the sdo pins. a 50mhz external clock must be applied at the sck pin to achieve 1.5msps throughput using all eight sdo1 through sdo8 outputs. clkout serial data clock output the clkout output provides a skew-matched clock to latch the sdo output at the receiver. the timing skew of the clkout and sdo outputs are matched. for high throughput applications, using clkout instead of sck to capture the sdo output eases timing requirements at the receiver. for low throughput speed applications, clkout can be disabled by tying pin 34 to ov dd . nap/sleep modes nap mode is a method to save power without sacrificing power-up delays for subsequent conversions. sleep mode has substantial power savings, but a power-up delay is incurred to allow the reference and power systems to become valid. to enter nap mode on the LTC2320-12, the sck signal must be held high or low and a series of two cnv pulses must be applied. this is the case for both cmos and lvds modes. the second rising edge of cnv initiates the nap state. the nap state will persist until either a single rising edge of sck is applied, or further cnv pulses are applied. the sck rising edge will put the LTC2320-12 back into the operational (full-power) state. when in nap mode, two additional pulses will put the LTC2320-12 in sleep mode. when configured for cmos i/o operation, a single rising edge of sck can return the ltc2320 -12 into operational mode. a 10ms delay is necessary after exiting sleep mode to allow the reference buffer to recharge the external filter capacitor. in lvds mode, exit sleep mode by supplying a fifth cnv pulse. the fifth pulse will return the ltc2320 -12 to operational mode, and further sck pulses will keep the part from re-entering nap and sleep modes. the fifth sck pulse also works in cmos mode as a method to exit sleep. in the absence of sck pulses, repetitive cnv pulses will cycle the LTC2320-12 between operational, nap and sleep modes indefinitely. refer to the timing diagrams in figure? 18, figure? 19, figure?20 and figure?21 for more detailed timing informa - tion about sleep and nap modes. figure?18. cmos and lvds mode nap and wake using sck full power mode 1 2 cnv sck hold static high or low nap mode sdo1 ? 8 wake on 1st sck edge z z 232012 f18 lt c2320-12 rev b
26 for more information www.analog.com applications information figure?19. cmos mode sleep and wake using sck figure?20. lvds and cmos mode sleep and wake using cnv figure?21. LTC2320-12 timing diagram full power mode 1 2 3 4 4.096v 4.096v refout recovery refout1 ? 4 cnv sck hold static high or low nap mode sleep mode sdo1 ? 8 wake on 1st sck edge z z z z 232012 f19 t wake 1 2 3 4 5 4.096v 4.096v refout recovery cnv sck hold static high or low nap mode sleep mode full power mode wake on 5th cnv edge z z z z z 232012 f20 t wake refout1 ? 4 sdo1 ? 8 232012 f21 lt c2320-12 rev b sdo 1 15 16 clkout d14 d2 d13 t conv t readout d15 d15 d0 d1 t dsckclkout t dcnvsdoz t hsdo t dcnvsdov hi-z hi-z t dsckcnvh t sckl ddr mode timing 1 15 16 2 2 3 3 14 14 t sckh 1 2 3 d15 14 15 16 t sckl t sckh t sck t sck t cnvh t cyc cnv sck sdo 1 2 3 14 15 t cnvh 16 clkout d14 d2 d13 t conv t readout d15 d0 d1 t cyc t dsckclkout t dcnvsdoz t hsdo t dcnvsdov hi-z hi-z t dsckcnvh sdr mode timing cnv sck
27 for more information www.analog.com applications information figure?22. LTC2320-12 using the lvds interface figure?23. LTC2320-12 using the lvds interface with one lane 100 2.5v 2.5v ov dd LTC2320-12 fpga or dsp 232012 f22 sck + sck ? sdod + sdod ? sdoc + sdoc ? sdob + sdob ? sdoa + sdoa ? cmos /lvds + ? + ? 100 + ? 100 + ? 100 + ? 100 + ? 100 clkout + clkout ? cnv retiming flip-flop 100 2.5v 2.5v ov dd LTC2320-12 fpga or dsp 232012 f23 sck + sck ? sdod + sdod ? sdoc + sdoc ? sdob + sdob ? sdoa + sdoa ? cmos /lvds + ? + ? 100 + ? 100 clkout + clkout ? cnv retiming flip-flop digital interface the ltc2320 -12 features a serial digital interface that is simple and straightforward to use. the flexible ov dd supply allows the LTC2320-12 to communicate with any digital logic operating between 1.8v and 2.5v . in addi - tion to a standard cmos spi interface, the LTC2320-12 provides an optional lvds spi inter face to support low noise digital design. the cmos /lvds pin is used to select the digital interface mode. the sck input clock shifts the conversion result msb first on the sdo pins. clkout provides a skew-matched clock to latch the sdo output at the receiver. the timing skew of the clkout and sdo outputs are matched. for high throughput applications, using clkout instead of sck to capture the sdo output eases timing requirements at the receiver. in cmos mode, use the sdo1 C sdo8, and clkout pins as outputs. use the sck pin as an input. in lvds mode, use the sdoa + / sdoa C through sdod + /sdod C and clkout + /clkout C pins as differential outputs. each lvds lane yields two channels worth of data: sdoa yields ch1 and ch2 data, sdob yields ch3 and ch4 data, sdoc yields ch5 and ch6 data and sdod yields ch7 and ch8 data. these pins must be differentially terminated by an external 100 resistor at the receiver (fpga). the sck + /sck C pins are differential inputs and must be terminated differentially by an external 100 resistor at the receiver(adc). lt c2320-12 rev b
28 for more information www.analog.com applications information sdr/ddr modes the ltc2320 -12 has an sdr (single data rate) and ddr (double data rate) mode for reading conversion data from the sdo pins. in both modes, clkout is a delayed version of sck. in sdr mode, each negative edge of sck shifts the conversion data out the sdo pins. in ddr mode, each edge of the sck input shifts the conversion data out. in ddr mode, the required sck frequency is half of what is required in sdr mode. tie sdr/ddr to ground to configure for sdr mode and to ov dd for ddr mode. the clkout signal is a delayed version of the sck input and is phase aligned with the sdo data. in sdr mode, the sdo transitions on the falling edge of clkout as illustrated in figure? 21. we recommend using the rising edge of clkout to latch the sdo data into the fpga register in sdr mode. in ddr mode, the sdo transitions on each input edge of sck. we recommend using the clkout ris - ing and falling edges to latch the sdo data into the fpga registers in ddr mode. since clkout and sdo data is phase aligned, the sdo signals will need to be digitally delayed in the fpga to provide adequate setup and hold timing margins in ddr mode. multiple data lanes the ltc2320 -12 has up to eight sdo data lanes in cmos mode and four sdo lanes in lvds mode. in cmos mode, the number of possible data lanes range from eight (sdo1?C ?sdo8), four (sdo1, sdo3, sdo5 and sdo7), two (sdo1 and sdo5) and one (sdo1). generally, the more data lanes used, the lower the required sck frequency. when using less than eight lanes in cmos mode, there is a limit on the maximum possible conversion frequency (see table 3). each sdo pin will hold the msb of the con - version data. in ddr mode you can use a sck frequency half the sdr mode. see table 3 for examples of various possibilities and the resulting sck frequency required. multiple data lanes the LTC2320-12 has up to eight serial data output data lanes in cmos mode and four serial data output lane pairs in lvds mode. the data on each lane consists of 12-bit conversion results presented msb first. cmos in cmos mode, the number of possible data lanes range from eight (sdo1 C sdo8), four (sdo1, sdo3, sdo5 and sdo7), two (sdo1 and sdo5) and one (sdo1). as suggested in the cmos timing diagrams, each sdo lane outputs the conversion results for all analog input chan - nels in a sequential circular manner. for example, the first conversion result on sdo1 corresponds to analog input channel 1, followed by the conversion results for chan - nels?2 through 8. the data output on sdo1 then wraps back to channel 1 and this pattern repeats indefinitely . other sdo lanes follow a similar circular pattern except the first conversion result presented on each lane corresponds to its associated analog input channel. applications that cannot accommodate the full eight lanes of serial data may employ fewer lanes without reconfigur - ing the LTC2320-12. for example, capturing the first two conversion results (32 sck cycles total in sdr mode and 32 sck edges in ddr mode) from sdo1, sdo3, sdo5, and sdo7 provides data for analog input channels 1 and 2, 3 and 4, 5 and 6, and 7 and 8, respectively , using four output lanes. similarly , capturing the first four conversion results (64 sck cycles total in sdr mode and 64 sck edges in ddr mode) from sdo1 and sdo5 provides data for analog input channels 1 to 4 and 5 to?8, respectively, using two output lanes. if only one lane can be accom - modated, capturing the first eight conversion results (128? sck cycles total in sdr mode and 128 sck edges in ddr mode) from sdo1 provides data for all analog input channels. generally, the more data lanes used, the lower the required sck frequency. when using less than eight lanes in cmos mode, there is a limit on the maximum possible conversion frequency. see table 3 for examples of various possibilities and the resulting sck frequency required. lvds in lvds mode, the number of possible data lane pairs range from four (sdoa C sdod), two (sdoa and sdoc) and one (sdoa). as suggested in the lvds timing diagrams, each sdo lane pair outputs the conversion results for all analog input channels in a sequential circular manner. lt c2320-12 rev b
29 for more information www.analog.com applications information for example, the first conversion result on sdoa cor - responds to analog input channel pair 1 and 2, followed by the conversion results for channels 3 through 8. the data output on sdoa then wraps back to channel 1 and this pattern repeats indefinitely . other sdo lanes follow a similar cir cular pattern except the first conversion result presented on each lane corresponds to its associated analog input channel pairs (sdoa: analog inputs 1 and 2, sdob: analog inputs 3 and 4, sdoc: analog inputs 5 and 6 and sdod: analog inputs 7 and 8). applications that cannot accommodate the full four lanes of serial data may employ fewer lanes without reconfigur - ing the LTC2320-12. for example, capturing the first four conversion results (64 sck cycles total in sdr mode and 64 sck edges in ddr mode) from sdoa and sdoc provides data for analog input channels 1 through 4, and 5 through 8, respectively, using two output lanes. if only one lane can be accommodated, capturing the first eight conversion results (128 sck cycles total in sdr mode and 128 sck edges in ddr mode) from sdoa provides data for all analog input channels. generally, the more data lanes used, the lower the required sck frequency. when using less than four lanes in lvds mode, there is a limit on the maximum possible conversion frequency. see table 3 for examples of various possibilities and the resulting sck frequency required. board layout to obtain the best performance from the LTC2320-12, a printed circuit board is recommended. layout for the printed circuit board (pcb) should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals adjacent to analog signals or underneath the adc. supply bypass capacitors should be placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. a single solid ground plane is recommended for this purpose. when possible, screen the analog input traces using ground. recommended layout for a detailed look at the reference design for this con - verter, including schematics and pcb layout, please refer to dc2395a , the evaluation kit for the LTC2320-12. table 3. conversion frequency for various i/o modes i/o mode cmos/ lvds pin sdr/ ddr pin sdo1 C 8 lanes sdoa C d lanes sck freq (mhz) clkout freq (mhz) sck cycles ov dd conversion frequency (msps/ch) cmos gnd (cmos) gnd (sdr) sdo1 C sdo8 100 100 16 1.8v to 2.5v 1.5 ov dd (ddr) sdo1 C sdo8 50 50 8 1.5 ov dd (ddr) sdo1, sdo3, sdo5, sdo7 50 50 16 1.25 gnd (sdr) sdo1 100 100 128 0.5 lvds ov dd (lvds) gnd (sdr) sdoa C sdod 200 200 32 2.5v 1.5 ov dd (ddr) sdoa C sdod 100 100 16 1.5 ov dd (ddr) sdoa, sdoc 150 150 32 1.4 gnd (sdr) sdoa 300 300 128 1.0 notes: conversion period (sdr) = t cnv_min + t conv_max + (128/(lanes ? f sck )) conversion period (ddr) = t cnv_min + t conv_max + (64/(lanes ? f sck )) conversion frequency = 1/conversion period sck cycles (sdr) = 128/lanes sck cycles (ddr) = 64/lanes lt c2320-12 rev b
30 for more information www.analog.com package description 7.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.30 typ or 0.35 45c chamfer 0.40 0.10 5251 1 2 bottom view?exposed pad top view side view 6.50 ref (2 sides) 8.00 0.10 (2 sides) 5.50 ref (2 sides) 0.75 0.05 0.75 0.05 r = 0.115 typ r = 0.10 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 6.45 0.10 5.41 0.10 0.00 ? 0.05 (ukg52) qfn rev ? 0306 5.50 ref (2 sides) 5.41 0.05 6.45 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 6.10 0.05 7.50 0.05 6.50 ref (2 sides) 7.10 0.05 8.50 0.05 0.25 0.05 0.50 bsc package outline ukg package 52-lead plastic qfn (7mm 8mm) (reference ltc dwg # 05-08-1729 rev ?) please refer to http://www.linear.com/product/LTC2320-12#packaging for the most recent package drawings. lt c2320-12 rev b
31 for more information www.analog.com revision history rev date description page number a 02/17 corrected text to specify no latency 17 b 03/18 corrected max specs for p d_3.3v and p d_5v in nap mode (missing decimal point) 5 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. lt c2320-12 rev b
32 for more information www.analog.com ? analog devices, inc. 2017-18 d16843 -0-4/18(b) www.analog.com related parts typical application part number description comments adcs ltc2310-16/ltc2310-14/ ltc2310-12 16-/14-/12-bit differential input adc with wide input common mode 3.3v/5v supply, single-channel, 35mw, 20ppm/c max internal reference, flexible inputs, 16-lead msop package ltc2321-16/ltc2321-14/ ltc2321-12 dual 16-/14-/12-bit, 2msps/ch, simultaneous sampling adcs 3.3v/5v supply, 33mw/ch, 20ppmc max internal reference, flexible inputs, 4mm 5mm qfn-28 package ltc2324-16/ltc2324-14/ ltc2324-12 quad 16-/14-/12-bit 2msps/ch simultaneous sampling adcs 3.3v/5v supply, single-channel, 40mw, 20ppm/c max internal reference, flexible inputs, 52-lead qfn package ltc2370-16/ltc2368-16/ ltc2367-16/ltc2364-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adcs 2.5v supply , pseudo-differential unipolar input, 94db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2380-16/ltc2378-16/ ltc2377-16/ltc2376-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adcs 2.5v supply , differential input, 96.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages dacs ltc2632 dual 12-/10-/8-bit, spi v out dacs with internal reference 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, 8-pin thinsot? package ltc2602/ltc2612/ ltc2622 dual 16-/14-/12-bit spi v out dacs with external reference 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, 8-lead msop package references ltc6655 precision low drift, low noise buffered reference 5v/4.096v/3.3v/3v/2.5v/2.048v/1.25v, 2ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift, low noise buffered reference 5v/4.096v/3.3v/3v/2.5v/2.048v/1.25v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers lt1818/ lt1819 400mhz, 2500v/s, 9ma single/dual operational amplifiers C85dbc distortion at 5mhz, 6nv/hz input noise voltage, 9ma supply current, unity-gain stable lt1806 325mhz, single, rail-to-rail input and output, low distortion, low noise precision op amps C80dbc distortion at 5mhz, 3.5nv/hz input noise voltage, 9ma supply current, unity-gain stable lt6200 165mhz, rail-to-rail input and output, 0.95nv/hz low noise, op amp family low noise, low distortion, unity-gain stable low jitter clock timing with rf sine generator using clock squaring/level-shifting circuit and retiming flip-flop nc7svu04p5x ( 9) 50 nc7svuo4p5x conv enable master_clock conv 1k 1k LTC2320-12 232012 ta02 sdo1 ? 8 sck gnd clr nc7sv74k8x control logic (fpga, cpld, dsp, etc.) pre clkout cnv cmos /lvds gnd sdr/ddr v cc v cc q d 0.1f 10 10 lt c2320-12 rev b

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